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typed PCI registers, virtio MAC randomization, SMP syscall trap#2367

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uadhran wants to merge 2 commits into
includeos:mainfrom
uadhran:fix/small-issue-trio
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typed PCI registers, virtio MAC randomization, SMP syscall trap#2367
uadhran wants to merge 2 commits into
includeos:mainfrom
uadhran:fix/small-issue-trio

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@uadhran

@uadhran uadhran commented Jun 10, 2026

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Tested: nix-build unittests.nix — 85/85 unit tests passed (Nix 2.34.7, Linux).

Not run yet: ./test/test.sh, integration/unikernel builds.


Three small fixes:

PCI config registers (#2333)
PCI register offsets were plain #defines in the header. Moved them to
enum classes (config_reg, command, cap_id) for type safety.
Updates in pci_device.cpp and pci_msi.cpp.

VirtioNet MAC (#1409)
QEMU hands out the same default MAC on every virtio-net device, which is
awkward when running multiple instances locally. After reading the MAC
from virtio config we randomize the host-specific bytes and set the
locally-administered bit. Uses RDRAND/RDSEED when available, with a
pci_addr + clock fallback (drivers init before RNG::init()).

SMP syscall trap (#2358)
Only CPU 0 had the syscall MSR set up. Pulled that into
init_syscall_trap() and call it from both the BSP libc init path
and revenant_main. Handler still panics — syscalls aren't
implemented — but APs get a trap instead of nothing.

Related: #2333, #1409, #2358

uadhran added 2 commits June 10, 2026 17:42
…P syscall trap

- Replace PCI config register #defines with typed enum classes (includeos#2333)
- Randomize virtio-net host MAC bytes on init to avoid local collisions (includeos#1409)
- Set up syscall trap on AP cores via shared init_syscall_trap() (includeos#2358)
Drivers initialize before RNG::init(), so rng_extract() was reading
uninitialized state. Use RDRAND/RDSEED when available, with a
pci_addr + clock fallback otherwise.
@uadhran uadhran marked this pull request as draft June 10, 2026 13:21
@uadhran uadhran changed the title hw: typed PCI registers, virtio MAC randomization, SMP syscall trap WIP: typed PCI registers, virtio MAC randomization, SMP syscall trap Jun 10, 2026
@uadhran uadhran changed the title WIP: typed PCI registers, virtio MAC randomization, SMP syscall trap typed PCI registers, virtio MAC randomization, SMP syscall trap Jun 11, 2026
@uadhran uadhran marked this pull request as ready for review June 11, 2026 06:13
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